Wafer-Level Micro/Nanosystems Integration and Packaging

Micro/nanosystems have attracted considerable interests and seen significant advances over the years. The huge gap between technology development and commercialization can be largely attributed to the challenges faced in the integration and packaging of the devices. The packaging has to work around the diverse functional requirements while ensuring that the device is able to perform effectively and reliably at the prescribed operating environments. The trend to make products lighter, smaller and thinner is relentless; heavy emphasis is placed on user-friendliness, functionality, durability and price competitiveness. Wafer bonding is recognized to be a key technology for three dimensional (3D) integration and packaging; particularly for micro/nanosystems that require vacuum packaging and hermetic sealing. The bonding process can be applied to a wide range of materials, including silicon, III–V semiconductor compounds, glass and ceramics. Low temperature bonding offers crucial advantages in multifunctional systems packaging such as system in packages (SIP). Low temperature bonding, through-via interconnection, metal-to-metal joining, alignment and hermeticity are a set of process challenges that have to be collectively overcome before we are likely to see pervasive applications of micro/nanosystems.